Decreasing the Power-Clock Resonant Signal Central Voltage as a Mean for Power Reduction in Integrated Power and Clock Distribution Networks

Background/Objectives: Density, performance, and design complexity of integrated circuits are rapidly increasing specifically in 3-D integration where multi-plane synchronization is required. The power clock distribution networks consume a large portion the limited on-chip metal resources. In order to reduce overhead associated with power, global clock, local networks, concept an network (IPCDN) was investigated correct functionality combinational sequential elements verified. This study discusses potential savings IPCDNs achieved by reducing central voltage at which signal oscillates. Methods/Statistical analysis: this paper, IPCDN differential power-clock signals centered half supply proposed further consumption. scheme including LC driver, clamping circuit, buffer, doubler have been simulated using Tanner 0.25 um CMOS technology frequency 50 MHz 2.5 V. Findings: Simulation results indicate that achieves 75.32% 76.47% reduction powerclock driver respectively. effects process, supply, temperature (PVT) variations on were also investigated. Discussion: has capacitance heavily loaded, thus resonant sinusoidal flowing enables significant Novelty/Applications: reductions buffer. all circuit Keywords: clocking; reduction; routing complexity; driver; buffer; circuit;